`timescale 1ns / 1ps
`default_nettype none


module traffic (
    input wire clk,
    output wire ns_red, ns_yellow, ns_green,
    output wire ew_red, ew_yellow, ew_green
);
    wire [5:0] ticks;
    dffe_Nbit #(.N(6)) ff (.clk(clk), .q(ticks), .d(ticks+1), .ena(1));
    assign ns_green = (ticks<30);
    assign ns_yellow = (ticks==30 || ticks==31);
    assign ew_green = (ticks>31 && ticks<62);
    assign ew_yellow = (ticks==62 || ticks==63);
    assign ns_red = ew_green || ew_yellow;
    assign ew_red = ns_green || ns_yellow;
endmodule


module dffe_Nbit #(parameter N=1)
(
    input  wire         clk,
    input  wire         ena,
    input  wire [N-1:0] d,
    output wire [N-1:0] q
 );
    reg [N-1:0] qreg=0;
    always @ (posedge clk) begin
        if (ena) qreg <= d;
    end
    assign q = qreg;
endmodule