`timescale 1ns / 1ps
`default_nettype none


module traffic_tb;
    // each input needs to be driven by a reg
    reg clk = 0;
    // each output needs to be connected to a wire
    wire ns_red, ns_yellow, ns_green, ew_red, ew_yellow, ew_green;
    // initantiate traffic module ("unit under test")
    traffic uut (.clk(clk), 
		 .ns_red(ns_red), .ns_yellow(ns_yellow), .ns_green(ns_green),
		 .ew_red(ew_red), .ew_yellow(ew_yellow), .ew_green(ew_green));
    // drive clock with 100ns period, first transition at 500ns
    initial begin
	#450;
        forever begin
            #50 clk = ~clk;
        end
    end
    // display traffic light outputs to console
    always @ (negedge clk) begin
        $display("time=%1d  NS r/y/g=%d/%d/%d  EW r/y/g=%d/%d/%d",
	         $time, 
		 ns_red, ns_yellow, ns_green,
		 ew_red, ew_yellow, ew_green);
    end
    // terminate simulation after 10000 ns
    initial begin
	#100000;
	$finish;
    end
endmodule