Sketch of board to remove "ghost" SVT tracks (as worked out on blackboard by Bill, Mel, and discussed at various 12/00 SVT meetings)

• Motivation/benefits

• Filter all but the one "best" SVT track corresponding to each XFT track

• When allowing one missing SVX-II layer in pattern recognition (instead of requiring hits in four specific layers), one algorithm ("4/5") will output five separate roads in the ~80% of cases in which all five layers have hits, and the other ("4*") may output many separate roads in the ~20% of cases in which one layer is missing a hit.

• Multiple hits within a superstrip can increase number of fitted tracks combinatorially.

• Want to minimize time needed to transfer SVT tracks to L2 processors (and number of tracks for L2 to process), so that L1 accepts can occur at full design rate

• Include no-op mode (pass data unchanged, with minimal latency)

• Build in capability for standard CDF DAQ readout

• Currently no SVT board implements the four L2 readout buffers

• Would allow readout into event record of data currently accessible only through spy buffers, e.g. hit lists, road lists

• Would allow SVT readout (e.g. for debug) even if the L2 decision crates were in use for other tests

• Could be inserted in the middle of any existing SVT cable

• Could be used as a diagnostic tool by L2/track interface board experts, e.g. to validate readout

• Another path for SVT to synchronize to CDF clock for readout and to receive L1A, L2B, bunch ID, if SVT is exercised in its own partition

• This functionality has been quite useful for testing, was essential for operating SVT in the commissioning run, but is currently provided in an unmaintainable way by a modified Hit Finder board

• Architecture

• VME interface, input logic (FIFOs, LVDS receivers), output logic (LVDS drivers) would be largely copied from Track Fitter board; VME interface of FADC board is actually closer to what we want, and includes trigger signals, etc.

• I think FIFOs are 18 bits wide, so two are needed, and cost $40 or $50 each; I'm guessing VME interface parts cost $50-100 total

• Using same parts makes it possible to build a prototype quickly, without parts delays; design re-use also speeds up the process, of course

• We think processing can be handled entirely by a single Altera APEX 20K200-series chip

• The chip used on FADC board is EP20K200BC356-1XV (the "V" means 5V-tolerant inputs, the "1" means fast, and the "X" means a PLL feature that we don't use, but that was what was available), for $325; we can probably use EP20K200BC356-3V, for $160.

• Has 200K gates available for logic, compared to 50K for HF clustering engines

• Has 106496 bits of internal RAM, which naively should be able to hold about 600 tracks (more than 2x the number (288) of XFT linker chips); in real life, there are some constraints on the widths/depths in which the memory can be used, but this should be plenty

• A 20K100-series chip may be able to do the job (half the RAM, half the gates, somewhat less than half the cost), but probably it pays to leave room for expansion

• Learn from and build upon experience of FADC board

• The basic design requires (beyond VME interface) two connectors, some small parts, and one big chip. Since an SVT front panel has room for six connectors, it may make sense to triplicate the basic unit

• Reduces latency of filtering operation through parallel processing of different wedges

• Allows more pieces of data stream to be debugged

• More cost effective, fewer VME slots, assuming you want more than one

• Since we have twelve Track Fitters, and Mergers have four inputs and two outputs, one could elegantly capture the output of all twelve Track Fitters into three parallel inputs, just before the "final" Merger that feeds the L2/track board

• Schedule

• First verify, using Quartus simulation, that a 20K200 chip's memory can be arranged and used in a way that solves duplicate problem

• Flesh out parts list, etc.; identify parts (if any) that do not overlap with other UofC projects

• Assess level of optimism, based on FADC board experience

• Steal pieces of schematic from TF and FADC boards; base I/O logic on that of other SVT boards' firmware

• Start layout, simulation

• Flesh out the firmware

• Aim for April 1 prototype delivery