SVT GhostBuster Board (WJA, 2001-02-05)

• Filter all but the one "best" SVT track corresponding to each XFT track

• Should reduce L2 processing time for non-4/4 SVT operation

• Use memory whose address is XFT linker number, data is full SVT track + small (9 bits?) track quality ranking

• Six connectors / FP ==> three parallel GBs / board (sits before final Merger)

• Fringe benefits

• Fulfill the "SVT board on a chip" dream that many of us have had for a while

• Implement the four L2 readout buffers (for debug data)

• Synchronize to CDF clock + L1A, provide L2B + bunch ID, when SVT is exercised in its own partition (replaces "XTRP emulator" kludge)

• Schedule

• Keep it simple: cut and paste pieces from SVT TF and COT FADC schematics

• All parts will already be in our spares supply, except for big (APEX 20K200) Altera chip, which overlaps with FADC project

• FADC prototype testing is going well, so we are optimistic about using APEX chip

• Mircea has checked, in Quartus (Altera), that 20K200 memory can be arranged to buffer one track / XFT linker chip

• We have been cleared by Fermilab to produce prototypes

• Need to do parts list, order parts, next week

• Mircea and I (mostly Mircea) will start to flesh out schematic once FADC board testing subsides a bit, in a week or so

• Aim to have prototype ready in April