// fourbit_fulladder_tb.v

`timescale 1ns / 1ps
`default_nettype none

module fourbit_fulladder_tb;
    // Inputs (for both v1 and v2 adders)
    reg        cin=0;
    reg  [3:0] a=0, b=0;
    // Outputs of fourbit_fulladder_v1
    wire [3:0] sum;
    wire       cout;
    // Outputs of fourbit_fulladder_v2
    wire       sum1, sum2, sum3, sum4, c4;

    // Instantiate the Unit Under Test (UUT) (both of them)
    fourbit_fulladder_v1 uut_v1
    (
	.c0(cin), 
	.a1(a[0]), .a2(a[1]), .a3(a[2]), .a4(a[3]),
	.b1(b[0]), .b2(b[1]), .b3(b[2]), .b4(b[3]),
	.sum1(sum1), .sum2(sum2), .sum3(sum3), .sum4(sum4), .c4(c4)
    );
    fourbit_fulladder_v2 uut_v2
    (
	.cin(cin), .a(a), .b(b),
	.sum(sum), .cout(cout)
    );

   integer i=0, j=0, k=0;
   initial begin
	#100;  // Wait 100 ns for simulator reset to finish
	for (i=0; i<2; i=i+1) begin
	    for (j=0; j<16; j=j+1) begin
		for (k=0; k<16; k=k+1) begin
		   cin = i;
		   a = j;
		   b = k;
		   #100;  // Wait 100 ns so that we can see output update
		end
	    end
	end
	$finish;
    end
endmodule