# lab9.ucf -- mapping Verilog names to FPGA pins

NET "pin01"  LOC="12" | IOSTANDARD=LVTTL ;
NET "pin02"  LOC="13" | IOSTANDARD=LVTTL ;
NET "pin03"  LOC="14" | IOSTANDARD=LVTTL ;
NET "pin04"  LOC="16" | IOSTANDARD=LVTTL ;
NET "pin09"  LOC="18" | IOSTANDARD=LVTTL ;
NET "pin10"  LOC="19" | IOSTANDARD=LVTTL ;
NET "pin11"  LOC="20" | IOSTANDARD=LVTTL ;
NET "pin12"  LOC="21" | IOSTANDARD=LVTTL ;
NET "pin13"  LOC="22" | IOSTANDARD=LVTTL ;
NET "pin14"  LOC="23" | IOSTANDARD=LVTTL ;
NET "pin15"  LOC="27" | IOSTANDARD=LVTTL ;
NET "pin16"  LOC="28" | IOSTANDARD=LVTTL ;
NET "pin17"  LOC="29" | IOSTANDARD=LVTTL ;
NET "pin18"  LOC="30" | IOSTANDARD=LVTTL ;
NET "pin22"  LOC="31" | IOSTANDARD=LVTTL ;
NET "pin23"  LOC="32" | IOSTANDARD=LVTTL ;
NET "pin24"  LOC="33" | IOSTANDARD=LVTTL ;
NET "pin25"  LOC="34" | IOSTANDARD=LVTTL ;
NET "pin26"  LOC="36" | IOSTANDARD=LVTTL ;
NET "pin27"  LOC="37" | IOSTANDARD=LVTTL ;
NET "pin28"  LOC="38" | IOSTANDARD=LVTTL ;
NET "pin29"  LOC="39" | IOSTANDARD=LVTTL ;
NET "pin30"  LOC="40" | IOSTANDARD=LVTTL ;
NET "pin31"  LOC="41" | IOSTANDARD=LVTTL ;
NET "pin32"  LOC="42" | IOSTANDARD=LVTTL ;
NET "pin33"  LOC="43" | IOSTANDARD=LVTTL ;
NET "pin34"  LOC="44" | IOSTANDARD=LVTTL ;
NET "pin35"  LOC="1"  | IOSTANDARD=LVTTL ;
NET "pin36"  LOC="2"  | IOSTANDARD=LVTTL ;
NET "pin37"  LOC="3"  | IOSTANDARD=LVTTL ;
NET "pin38"  LOC="5"  | IOSTANDARD=LVTTL ;
NET "pin39"  LOC="6"  | IOSTANDARD=LVTTL ;
NET "pin40"  LOC="8"  | IOSTANDARD=LVTTL ;