/*
 * lab9.v
 * Skeletal program from which to begin PHYS364 Lab 9
 * begun 2010-11-04 by Bill Ashmanskas, ashmansk@hep.upenn.edu
 */

`timescale 1ns / 1ps
`default_nettype none


module lab9
(
   /*
    * I chose these dumb names for the I/O signals
    * so that the mapping to pin numbers on the CMOD
    * DIP package is obvious.  Normally you would
    * give the I/O pins mnemonic names and would put
    * them into the .ucf file accordingly.
    */
    input  wire pin01, pin02, pin03, pin04,
    input  wire pin09, pin10, pin11, pin12, pin13,
    input  wire pin14, pin15, pin16, pin17, pin18,
    output wire pin22, pin23, pin24, pin25, pin26,
    output wire pin27, pin28, pin29, pin30, pin31,
    output wire pin32, pin33, pin34, pin35, pin36,
    output wire pin37, pin38, pin39, pin40
);
    nand_etc nand_etc_instance (
        .a(pin02), .b(pin03),
	.not_a(pin22), .a_nand_b(pin23), 
	.a_and_b(pin24), .a_or_b(pin25), .a_xor_b(pin26));
    fourbit_fulladder fourbit_fulladder_instance (
        .cin(pin04), 
        .a({pin13,pin12,pin11,pin10}), 
        .b({pin17,pin16,pin15,pin14}),
	.sum({pin30,pin29,pin28,pin27}), .cout(pin31));
    decoder decoder_instance (
        .e1(0), .e2(0), .e3(pin01), .a({pin04,pin03,pin02}),
	.o({pin39,pin38,pin37,pin36,pin35,pin34,pin33,pin32}));
endmodule


module nand_etc
(
    input  wire a,
    input  wire b,
    output wire not_a,
    output wire a_nand_b,
    output wire a_and_b,
    output wire a_or_b,
    output wire a_xor_b
);
    assign not_a    = ~a;
    assign a_nand_b = ~(a&b);
    assign a_and_b  = a&b;
    assign a_or_b   = a|b;
    assign a_xor_b  = a^b;
endmodule


module fourbit_fulladder
(
    input  wire       cin,
    input  wire [3:0] a,
    input  wire [3:0] b,
    output wire [3:0] sum,
    output wire       cout
);
    assign {cout,sum} = a+b+cin;
endmodule


module decoder
(
    input  wire       e1, e2, e3,
    input  wire [2:0] a,
    output wire [7:0] o
);
    // Selected output is HIGH if E3 & not E2 & not E1; else LOW
    wire e = e3 & ~e2 & ~e1;
    // Drive selected output to 'e'; others to LOW
    assign o[0] = (a==0 ? e : 0);
    assign o[1] = (a==1 ? e : 0);
    assign o[2] = (a==2 ? e : 0);
    assign o[3] = (a==3 ? e : 0);
    assign o[4] = (a==4 ? e : 0);
    assign o[5] = (a==5 ? e : 0);
    assign o[6] = (a==6 ? e : 0);
    assign o[7] = (a==7 ? e : 0);
    // Note that I made the outputs active high here,
    // whereas the 74LS138 outputs are active low
endmodule