/*
 * lab9_demo.v
 * Skeletal program from which to begin PHYS364 Lab 9
 * begun 2010-11-04 by Bill Ashmanskas, ashmansk@hep.upenn.edu
 */


`timescale 1ns / 1ps

module lab9_demo
  (
   /*
	 * I choose these dumb names for the I/O signals
	 * so that the mapping to pin numbers on the CMOD
	 * DIP package is obvious.  Normally you would
	 * give the I/O pins mnemonic names and would put
	 * them into the .ucf file accordingly.
	 */
   input  wire pin01, pin02, pin03, pin04,
   input  wire pin09, pin10, pin11, pin12, pin13,
   input  wire pin14, pin15, pin16, pin17, pin18,
   output wire pin22, pin23, pin24, pin25, pin26,
   output wire pin27, pin28, pin29, pin30, pin31,
   output wire pin32, pin33, pin34, pin35, pin36,
   output wire pin37, pin38, pin39, pin40
   );
   wire clk = pin01;
   /*
    * 'count' will be an 11-bit counter, synchronous to the 'clk' input, which is
    * DIP pin 1.  We display the counter value on DIP pins 30-40.
    */
   reg [10:0] count = 0;
	always @ (posedge clk) begin
     count <= count+1;
	end
	assign pin40 = count[0];
	assign pin39 = count[1];
	assign pin38 = count[2];
	assign pin37 = count[3];
	assign pin36 = count[4];
	assign pin35 = count[5];
	assign pin34 = count[6];
	assign pin33 = count[7];
	assign pin32 = count[8];
	assign pin31 = count[9];
	assign pin30 = count[10];
endmodule