/*
 * lab9_synchronous.v
 * Skeletal program from which to begin PHYS364 Lab 9 (part 2)
 * begun 2010-11-04 by Bill Ashmanskas, ashmansk@hep.upenn.edu
 */

`timescale 1ns / 1ps
`default_nettype none


module lab9_synchronous
(
   /*
    * I chose these dumb names for the I/O signals
    * so that the mapping to pin numbers on the CMOD
    * DIP package is obvious.  Normally you would
    * give the I/O pins mnemonic names and would put
    * them into the .ucf file accordingly.
    */
    input  wire pin01, pin02, pin03, pin04,
    input  wire pin09, pin10, pin11, pin12, pin13,
    input  wire pin14, pin15, pin16, pin17, pin18,
    output wire pin22, pin23, pin24, pin25, pin26,
    output wire pin27, pin28, pin29, pin30, pin31,
    output wire pin32, pin33, pin34, pin35, pin36,
    output wire pin37, pin38, pin39, pin40
);
    counter counter_instance (
        .clk(pin01),
        .o({pin40,pin39,pin38,pin37,pin36,pin35}));
    shiftreg shiftreg_instance (
	.clk(pin01), .d(pin02),
        .o({pin34,pin33,pin32,pin31,pin30,pin29}));
endmodule


module counter
(
    input  wire       clk,
    output wire [5:0] o
);
    reg [5:0] oreg=0;
    always @ (posedge clk) begin
        oreg <= oreg+1;
    end
    assign o = oreg;
endmodule


module shiftreg
(
    input  wire       clk,
    input  wire       d,
    output wire [5:0] o
);
    reg [5:0] oreg=0;
    always @ (posedge clk) begin
        oreg[5] <= oreg[4];
        oreg[4] <= oreg[3];
        oreg[3] <= oreg[2];
        oreg[2] <= oreg[1];
        oreg[1] <= oreg[0];
        oreg[0] <= d;
    end
    assign o = oreg;
endmodule