// nand_etc_tb.v

`timescale 1ns / 1ps
`default_nettype none

module nand_etc_tb;
    // Inputs for UUT
    reg a=0;
    reg b=0;
    // Outputs of UUT
    wire not_a;
    wire a_nand_b;
    wire a_and_b;
    wire a_or_b;
    wire a_xor_b;

    // Instantiate the Unit Under Test (UUT)
    nand_etc uut 
    (
	.a(a), 
	.b(b), 
	.not_a(not_a), 
	.a_nand_b(a_nand_b), 
	.a_and_b(a_and_b), 
	.a_or_b(a_or_b), 
	.a_xor_b(a_xor_b)
    );

initial begin
    // Wait 100 ns for simulator reset to finish
    #100;  

    // Drive first set of inputs
    a = 0; b = 0;

    // Wait 100ns then drive next set of inputs
    #100; a = 1; b = 0;

    // Wait 100ns then drive next set of inputs
    #100; a = 0; b = 1;

    // Wait 100ns then drive last set of inputs
    #100; a = 1; b = 1;

    // Wait 100ns then terminate simulation
    #100;
    $finish;
end

endmodule