// shiftreg.v

`timescale 1ns / 1ps
`default_nettype none

module shiftreg
(
    input  wire       clk,
    input  wire       d,
    output wire [5:0] o
);
    reg [5:0] oreg=0;
    always @ (posedge clk) begin
        oreg[5] <= oreg[4];
        oreg[4] <= oreg[3];
        oreg[3] <= oreg[2];
        oreg[2] <= oreg[1];
        oreg[1] <= oreg[0];
        oreg[0] <= d;
    end
    assign o = oreg;
endmodule