// shiftreg_tb.v

`timescale 1ns / 1ps
`default_nettype none

module shiftreg_tb;
    // Inputs for shiftreg
    reg        clk=0, d=0;
    // Outputs of shiftreg
    wire [5:0] o;

    // Instantiate the Unit Under Test (UUT)
    shiftreg uut
    (
        .clk(clk), .d(d),
        .o(o)
    );

   integer i=0;
   initial begin
	#100;  // Wait 100 ns for simulator reset to finish
	for (i=0; i<20; i=i+1) begin
            // Send in a short pulse at i=0 and a longer pulse at i=10
            d = (i==0 || i==10 || i==11);
	    #100;  // Wait 100 ns, jiggle the clock, and wait another 100 ns
            clk = 1;
	    #100;
            clk = 0;
	end
	$finish;
    end
endmodule